Given a linked list which happens to sit on consecutive memory, traversing it can take advantage of L1 cache. However it's possible to squeeze more performance by hinting the branch predictor to allow speculative execution, resulting in better parallelism with cpu pipeline. This is a simple and interesting trick although I can't think of much practical uses except for specific scenarios.

A nice article on the exploration of a performance issue, which ultimately leads to the discovery of a bug in AMD CPU.

Kernel schedules to pid 0 on idle, which issues the "halt" instruction (x86) to cause the cpu to stop working. There is a "dynamic tick" technique that don't wake up cpu on a fixed period but rather can be programmed to wake up at some time. The technique is used on mobile processors.

Interesting article comparing x86 with other IA by Raymond C.

Also see: https://devblogs.microsoft.com/oldnewthing/20220418-00/?p=106489 (The x86 architecture is the weirdo, part 2)